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Costas J. Spanos received his Electrical Engineering Diploma from the National Technical University of Athens, Greece in 1980 and his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University in 1981 and 1985, respectively. From 1985 to 1988, he was part of the advanced Computer-Aided Design group at Digital Equipment Corporation, where he worked on statistical characterization, simulation, and diagnosis of VLSI processes. In 1988, he joined the faculty of the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He served as Director of the Berkeley Microfabrication Laboratory from 1994 to 2000 and as Director of the Electronics Research Laboratory from 2004 to 2005. He was also the Associate Dean for Research in the College of Engineering from 2004 to 2008 and served as Associate Chair of the EECS Department and then Chair until June 2012. Spanos has published over 200 refereed articles, has served on technical committees for numerous conferences, and was an editor for IEEE Transactions on Semiconductor Manufacturing from 1991 to 1994. He was elected a Fellow of the Institute of Electrical and Electronic Engineers in 2000 for his contributions and leadership in semiconductor manufacturing. His current research interests include statistical analysis applications in integrated circuit design and fabrication, and the development and deployment of novel sensors and computer-aided techniques for semiconductor manufacturing.
University of California, Berkeley • Berkeley, CA
Professor Emeritus in the Department of Electrical Engineering and Computer Sciences.
Patent related to process control in semiconductor manufacturing.
Patent focused on optimizing semiconductor manufacturing process.
The Mathematics Subject GRE is required for the Fall 2026 admissions cycle. General GRE is optional.