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Nagarajan Raghavan obtained his Ph.D. in Microelectronics in 2012 from the Division of Microelectronics at Nanyang Technological University (NTU), Singapore. He also holds a Master’s degree in Advanced Materials Micro & Nano Systems (2008) and a Master’s degree in Materials Science Engineering (2008) from the National University of Singapore (NUS) and the Massachusetts Institute of Technology (MIT), respectively. Raghavan completed a post-doctoral fellowship at the Interuniversity Microelectronics Center (IMEC) in joint association with Katholieke Universiteit Leuven (KUL) in Belgium from 2012 to 2013, and subsequently participated in the SUTD-MIT Joint Postdoctoral Fellowship program from 2013 to 2015. His research focuses on reliability modeling of nanodevices, physics of failure modeling, maintenance engineering, and design reliability for prognostics and system health management. He has authored or co-authored close to 100 international peer-reviewed publications and holds a patent for co-inventing a CMOS platform to fabricate Resistive RAM devices. He has been a member of the IEEE since 2005 and served in various capacities including as an invited member of the IEEE GOLD committee from 2012 to 2014.
Katholieke Universiteit Leuven • Belgium
Conducted research in reliability modeling of nanodevices.
SUTD / MIT • Singapore
Involved in joint research projects focusing on system health management and maintenance engineering.
Patent related to Resistive RAM fabrication technology.
This applies to PhD programs in Architecture and Sustainable Design (ASD), Engineering Product Development (EPD), Engineering Systems and Design (ESD), Information Systems Technology and Design (ISTD), Science, Mathematics and Technology (SMT), and Humanities, Arts and Social Sciences (HASS).