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Paolo Ienne is a Professor at École Polytechnique Fédérale de Lausanne (EPFL) since 2000, where he leads the Processor Architecture Laboratory (LAP). Before joining EPFL, he worked in the Semiconductors Group of Siemens AG in Munich, Germany, which later became Infineon Technologies AG, where he headed the Embedded Memories unit of the Design Libraries division. His research interests encompass computer processor architecture, reconfigurable computing using FPGAs, electronic design automation, and computer arithmetic. Ienne has received several paper awards at prominent conferences in his field, including the ACM/SIGDA International Symposia on Field-Programmable Gate Arrays (FPGA) and the International Conference on Field-Programmable Logic Applications (FPL). He has also served in various leadership roles at renowned international conferences and has guest edited special issues in IEEE and ACM journals. As an associate editor of ACM Transactions on Architecture and Code Optimization, he contributes to the advancement of research in design automation, computer architecture, and embedded systems. Ienne is committed to the education and mentorship of students, having supervised numerous PhD candidates at EPFL.
Standard requirements for Engineering and Basic Science Master's programs. Architecture requires an additional portfolio.