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Paolo Ienne is a Professor at the École Polytechnique Fédérale de Lausanne (EPFL) since 2000, where he heads the Processor Architecture Laboratory (LAP). His prior experience includes working with Siemens AG in Munich, Germany, which later became Infineon Technologies AG, as the head of the Embedded Memories unit in the Design Libraries division. His research interests focus on various aspects of computer processor architecture, including Field-Programmable Gate Arrays (FPGAs), reconfigurable computing, electronic design automation, and computer arithmetic. Ienne has received numerous Paper Awards at prestigious conferences, including ACM/SIGDA International Symposia on Field-Programmable Gate Arrays and International Conferences on Field-Programmable Logic Applications. He has been actively involved in organizing and chairing various international conferences and workshops in his field, serves on the steering committee for ACM/SIGDA Symposium on FPGAs and IEEE Symposium on Computer Arithmetic, and guest-edited special issues in notable journals. Ienne's teaching also includes supervising PhD students and leading courses on advanced computer architecture and design principles.
Standard requirements for Engineering and Basic Science Master's programs. Architecture requires an additional portfolio.